1. Field of the Invention
The present invention generally relates to a semiconductor device having a multilayered metal interconnection structure and, more specifically, to a semiconductor device having a multilayered metal interconnection structure with improved flatness of an interlayer insulating film. The present invention also relates to a method of manufacturing such a semiconductor device having multilayered metal interconnection structure.
2. Description of the Background Art
Recently, semiconductor devices represented by dynamic random access memories (DRAMs), microprocessor unit (MPUS) and so on come to be ever and ever miniaturized and integrated to higher degree. Especially, in logic semiconductor devices such as MPU, there is a strong demand of higher speed of operation. For this reason, a technique for providing multiple layers of electrode interconnections connecting elements to each other has become essential.
FIG. 9 is a cross sectional view of a conventional logic device.
Referring to FIG. 9, a conventional logic device includes a semiconductor substrate 101 formed of a P type Si single crystal. At a main surface of semiconductor substrate 101, there is provided a field oxide film 102 for separating an active region from another active region. In the active region, source/drain regions 103 doped with N type impurity are provided. Further, in the active region, a gate oxide film 104a and gate electrode 104b formed of polycrystalline silicon obtained by CVD method (chemical vapor deposition) are formed. In a device of which high performance is required, a salicide layer 105 is provided on source/drain regions 103 in order to reduce contact resistance. Salicide layer 105 is formed of a metal salicide layer (generally, TiSi.sub.2, CuSi.sub.2, NiSi.sub.2 or the like) formed in self-alignment. In order to reduce resistance at gate electrode 104b, salicide layer 105 is also provided on gate electrode 104b.
Source/drain regions 103, gate oxide film 104a, gate electrode 104b and salicide layer 105 constitute an MOS (metal oxide semiconductor) transistor 401. One or a plurality of layers of metal interconnections for connecting transistors to each other are formed as needed. In the logic device shown in FIG. 9, there are four layers of metal interconnection, for example.
An interlayer insulating film 106 formed of BPSG (silicate glass including boron and phosphorus) or the like is formed on semiconductor substrate 101 to cover MOS transistor 401. In interlayer insulating film 106, a contact hole 107 for exposing a portion of the surface of source/drain region 103 is provided. In contact hole 107, an W plug 108b is provided, to be connected to source/drain region 103 with barrier metal 108a interposed. An interconnectIon 109 is provided on interlayer insulating film 106 to be in contact with W plug 108b. In order to pattern Al alloy interconnection 109 precisely and finely, an anti-reflection film 110 formed of TiN or the like is generally formed on Al interconnection 109.
A combination of contact hole 107, Al alloy interconnection 109 and anti-reflection film 110 will be hereinafter referred to as a first Al interconnection 402. A silicon oxide film 111 is formed on interlayer insulating film 106 by plasma CVD method, to cover the first Al interconnection 402. A silicon oxide film 112 referred to as spin on glass (hereinafter referred to as SOG) is provided to fill concave portions on the surface of silicon oxide film 111. On silicon oxide film 111, a second layer of silicon oxide film 113 formed by plasma CVD is provided. By a combination of silicon oxide films 111, 112 and 113, a first interlayer insulating film 403 having superior flatness and high electrical breakdown voltage is formed.
Thereafter, in the similar manner, a second Al interconnection 404, a third Al interconnection 406, a fourth Al interconnection 408, a second interlayer insulating film 405 and a third interlayer insulating film 407 are provided. On the uppermost layer of Al interconnection (the fourth Al interconnection 408 in FIG. 9), a passivation film 117 formed of a silicon oxide film, a silicon nitride film or a composite film thereof formed by plasma CVD is provided as a protection film.
The problems experienced by the conventional semiconductor device having multilayered interconnections will be described in the following.
Referring to FIG. 9, at a steep step denoted by the reference numeral 410, it is likely that residue remains at the time of etch back of tungsten and at the time of etching to form the pattern of Al interconnection. Such metal residue may cause short-circuit between interconnection, resulting in defective semiconductor devices.
Further, as denoted by reference numeral 411 in FIG. 9, part of the Al interconnection may be made thin, disconnected or made thick, resulting in short-circuit (in FIG. 9, an example of thinned interconnection is shown). Such thinning is derived from the fact that the step exceeds the depth of focus at the time of transfer and desired resist pattern could not be obtained because of this excess.
Further, as denoted by the reference number 412 in FIG. 9, there may be unsatisfactory opening of a via hole connecting upper and lower layers of Al interconnection, hindering satisfactory electrical connection. This is also caused by the step exceeding the depth of focus at the time of transfer, resulting in unsatisfactory resist pattern.
How the aforementioned problems occur will be described with reference to the flow chart of manufacturing the semiconductor device shown in FIG. 9.
Referring to FIG. 10, on the main surface of P type silicon substrate 101, a field oxide film 102, source/drain regions 103, a gate electrode 104 of polycrystalline silicon, a salicide layer 105 of TiSi.sub.2, CoSi.sub.2 or the like and interlayer insulating film 106 formed of BPSG are formed. In interlayer insulating film 106, contact hole 501 for exposing a portion of the surface of source/drain regions 103 is formed. Contact hole 501 is formed by using the technique of transfer and etching.
Referring to FIG. 11, a barrier metal 502 formed of TiN is provided by sputtering on silicon substrate 101, such that it is in contact with source/drain region 103 through contact hole 501. Barrier metal 502 serves as an adhesion layer to provide superior ohmic contact with silicon substrate to improve adhesion between W layer to be formed in the next step and the underlining interlayer insulating film. A W layer 503 is formed by CVD method on barrier metal 502 to fill contact hole 501. By setting the film thickness of W layer 503 to be at least the radius of contact hole 501, W layer 503 fully fills the contact hole 501.
Referring to FIGS. 11 and 12, W layer 503 is etched back entirely by reactive iron etching (RIE method) using a gas of SF.sub.6 or the like. This etching is stopped when the surface of barrier metal layer 502 appears, and thus a tungsten plug 504 is formed in contact hole 501, with W layer left only in the contact hole. After the formation of tungsten plug 504, an Al alloy layer 505 is formed by sputtering on silicon substrate 101.
For the Al type alloy 505, generally, an alloy such as Al-0.5 wt % Cu, Al-1 wt % Si-0.5 wt % Cu or the like is used. A small amount of Cu is added in order to improve electro-migration resistance of the interconnection. On Al alloy layer 505, an anti-reflection film 506 such as TiN is formed. Anti-reflection film 506 is to prevent halation at the time of transfer for forming Al interconnection, and hence to form highly precise fine interconnection. Appropriate film thickness of anti-reflection film 506 depends on the exposure apparatus (wavelength of the light source) and the resist. However, it is within the range of from 200 to 600 .ANG..
Referring to FIG. 13, by RIE method using a gas of Cl.sub.2 or the like, a first Al interconnection 507 is formed. Thereafter, by plasma CVD method, an interlayer insulating film 508 is formed on silicon substrate 101 to cover the first aluminum interconnection 507. The interlayer insulating film 508 is formed by plasma CVD method using tetraethyl ortho silicate (Si(OC.sub.2 H.sub.5).sub.4) (hereinafter referred to as TEOS) and O.sub.2. As compared with a film formed by plasma CVD using silane (SiH.sub.4) and O.sub.2, this film has superior step coverage.
Referring to FIG. 14, SOG (509) is applied on silicon substrate 101 and calcined. SOG is a material including silanol (Sl(OH).sub.4) solved in alcohol, which is a solvent. SOG turns to silicon oxide film (hereinafter referred to as SOG layer) as it is applied and then calcined. Since SOG is in liquid phase when it is applied, it fills trenches of the pattern with priority. As a result, silicon oxide film is formed at first in the trench portions, an hence flatness can be improved.
Referring to FIGS. 14 and 15, SOG layer 509 is etched back by RIE using a gas of CF.sub.4 +CHF.sub.3 +O.sub.2 or the like. The reason why the etch back is carried out is as follows. More specifically, SOG film 509 has inferior film quality as compared with a film formed by conventional CVD method, electric breakdown voltage is inferior and gas is emitted from the film. Therefore, it is necessary to remove SOG layer 509 formed at portions other than the trench.
Thereafter, the first silicon oxide film layer 510 is formed again by plasma CVD, and thus a first interlayer insulating film between Al interconnections is formed.
Referring to FIG. 16, in the similar manner, the second Al interconnection 511 and a second interlayer insulating film 512 between Al interconnections are formed.
Then, referring to FIG. 17, on the first interlayer insulating film 512 between Al interconnections, a third Al interconnection 513 is formed.
The problem of the prior art will be described.
Referring to FIGS. 16 and 17, flattening of interlayer insulating film between Al interconnections utilizing SOG is effective in flattening portions which have dense Al pattern. However, when the Al pattern is not dense, there would be a step of D1, for example, in the cross-section of FIG. 15. Further, when an interlayer insulating film between Al interconnection and upper layer of Al interconnection is formed, there would be a larger step denoted by D.sub.2, as shown in FIG. 16. If the upper layer of Al interconnection is formed with such a large step of D.sub.2 left as it is, the following problem occurs. Namely, referring to FIG. 17, when the third Al interconnection 513 is formed, there would be residue 514 of W layer at the step. The residue 514 causes short circuit between interconnections. Further, if the step D2 exceeds the depth of focus at the time of photolithography for forming interconnections, there would be defective pattern such as denoted by the reference numeral 515 in the figure.